1. Field of the Invention
The present invention relates to a subsidiary digital signal process for recovering the dynamic range of an input signal from the result of the main digital signal process which is executed with a bit width that is smaller than that of an input signal.
2. Description of the Related Art
With the advent of high-speed and high-accuracy CPUs (Central Processing Units) and DSPs (Digital Signal Processors), calculating processes for signals have been remarkably improved. Because of the improvement of the performance of the CPUs and DSPs, the overall signal processes are performed at high speeds. On the other hand, in order to further increase the calculation speed, newer types of CPUs and DSPs have been developed. For the same purpose, new instruction sets have also been developed. It is expected that the performance of digital signal processes will be improved with the newer forthcoming CPUs and DSPs.
As the performance of such CPUs and DSPs is improved, high-performance A/D converters and D/A converters as peripheral units are required. As one example of A/D converters, Japanese Patent Laid-Open Publication No. 6-152417 discloses an A/D converter used in a modem which over-samples an input signal to output a signal which is free from calculation error due to truncation and is of high S/N ratio. Additionally, this A/D converter changes its dynamic range according to the power of the input signal.
In this related art reference, when the bit width of an output signal of a down-sampling circuit in the A/D converter is larger than the bit width of an output signal of the A/D converter, the output signal of the down-sampling circuit is truncated so that the bit width thereof matches the bit width of the output signal.
When the bit width of the final output signal is 16 bits, there are two types of truncation methods. One of the two types of truncation methods is selected in an alternative way corresponding to the power detected in a predetermined time period. As one of the two types, the output signal of the down-sampling circuit is leftwardly shifted by a predetermined bit width and truncated into 16-bit data. As the other type, the output signal of the down-sampling circuit is rightwardly shifted into 16-bit data. According to the forementioned related art reference, with the two types of truncation methods, the dynamic range is changed corresponding to the power of the input signal.
In the related art reference, the gain is adjusted after the analog signal is input to the A/D converter and digitized. In the case that the digital audio signal is processed by fixed-point calculations on a CPU or DSP and the bit width of the input audio data is equal to the bit width of the output digital audio signal and the bit width of data of the internal calculations is smaller than the bit width of the input/output data, if the input data is bit-shifted and truncated into the bit width equal to that of the internal calculations, the gain of the final digital audio data is decreased in comparison with the gain of the input data. Thus, the output gain becomes smaller than the input gain.
Therefore, the output gain of the digital audio signal process should be adjusted to match to the input gain.
When the CPU that can execute the same fixed-point calculations of a certain number of bit in parallel is used, the calculations can be performed at high speed. However, if the bit width of the parallel calculations is different from the bit width of the input data, the parallel calculations cannot be performed. Thus, to perform the parallel calculation, the input data must be truncated within the bit width of the parallel calculations.